High-Performance Extendable Instruction Set Computing

111 this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset arid imniediate operands can be extended to 32 bits via the operation of an extension Jag. The code den& of the ElSC instruction set and its memoly transfer performance is shown to be significantly higher than current architectures making it a suitable candidate for the next generation of embedded computer systems. The compact EISC instruction set introduces data dependencies that seemingly limit deep pipeline and superscalar implementations., This paper suggests a mechanism by which these dependencies might be removed in hardware.